Abstract As user applications continue to drive network growth and evolution, demand to support different types of traffic is also increasing. Different types of applications with differing network requirements create a need for administrative policies mandating how individual applications are to be treated by the network. Network traffic from business-critical applications must be protected from other types of traffic. Requests from business-critical and delay-sensitive applications must be serviced with priority. The employment and enforcement of quality of service (QoS) policies within a network play an essential role in enabling network administrators and architects to meet networked application demands. QoS is a crucial element of any administrative policy that mandates how to handle application traffic on a network. Networks must provide secure, predictable, measurable, and, sometimes, guaranteed services. Network administrators and architects can better achieve this performance from network by managing delay, delay variation (Jitter), bandwidth provisioning, and packet loss parameters with quality of service (QoS) techniques. As the concept of converged network is being widely used today where all types of traffic are required to be sent and transmitted on the same wide area network (WAN) link. Hence different applications need to be differentiated and treated according to their sensitivity to business. QoS is the suitable answer and method to solve this issue and make sure that each traffic type will be treated differently using various mechanisms of QoS. In this research different types of traffic that represent different applications are generated in WAN and local area network (LAN) where various techniques of QoS are implemented. Network performance is indicated by capturing different parameters on real time such as, delay, jitter, packet loss, and bandwidth. Based on results obtained, a set of recommendations is concluded for each QoS mechanism highlighting the suitable traffic type for this technique to be used for along with appropriate network locations for this technique to be implemented.
نسرين عادل بن لطيف (2011)

https://theses.gla.ac.uk/3406/Parallelization has moved in recent years into the mainstream compilers, and the demand for parallelizing tools that can do a better job of automatic parallelization is higher than ever. During the last decade considerable attention has been focused on developing programming tools that support both explicit and implicit parallelism to keep up with the power of the new multiple core technology. Yet the success to develop automatic parallelising compilers has been limited mainly due to the complexity of the analytic process required to exploit available parallelism and manage other parallelisation measures such as data partitioning, alignment and synchronization. This dissertation investigates developing a programming tool that automatically parallelises large data structures on a heterogeneous architecture and whether a high-level programming language compiler can use this tool to exploit implicit parallelism and make use of the performance potential of the modern multicore technology. The work involved the development of a fully automatic parallelisation tool, called VSM, that completely hides the underlying details of general purpose heterogeneous architectures. The VSM implementation provides direct and simple access for users to parallelise array operations on the Cell’s accelerators without the need for any annotations or process directives. This work also involved the extension of the Glasgow Vector Pascal compiler to work with the VSM implementation as a one compiler system. The developed compiler system, which is called VP-Cell, takes a single source code and parallelises array expressions automatically. Several experiments were conducted using Vector Pascal benchmarks to show the validity of the VSM approach. The VP-Cell system achieved significant runtime performance on one accelerator as compared to the master processor’s performance and near-linear speedups over code runs on the Cell’s accelerators. Though VSM was mainly designed for developing parallelising compilers it also showed a considerable performance by running C code over the Cell’s accelerators.
Youssef Omran Gdura(5-2012)

Abstract The dynamic model of the heat process trainer PT326 is obtained experimentally by using the Ziegler–Nichols approximation and the system identification MATLAB toolbox. The interfacing data acquisition card is developed in two different designs the first design by using analog to digital, digital to analog IC's (ADC and DAC) and the parallel port, and the other design by using microcontroller and serial port. These two designs were tested in the department and give good results. The velocity PID controller is implemented through the developed cards in real time control system. An adapted neural network algorithm using the backpropagation approximation is tested on real time in the heat process trainer PT326. This research gives a good background for any control and computer engineer in the area of data acquisition and real time control system. The simulation results are the same as the online results of the real time Heat process control system.
نوري احمد عقاب (2010)