التسجيل باستخدام شبكة الإنترنت لجامعة طرابلس للطلاب المسجلين، و الطلبة الجدد و أعضاء هيئة التدريس، سوف يجعلهم قادرون للوصول إلي النظام، وإجراء العديد من الأنشطة كإضافة / إسقاط فصل دراسي، عرض جدول المحاضرات، عرض الفصول التي انتهي التسجيل فيها,عرض قوانين الجامعة. لقد تم تطوير النظام ليخدم حركة تسجيل الطلاب للمواد و جعلها عن طريق الإنترنت في جامعه طرابلس بغرض تسريع وتسهيل عملية التسجيل للطالب. يقوم قسم التسجيل بالتعامل مع الطالب بحيث يقوم بتسجيل المواد و منحه الوزن المناسب من الساعات في بداية كل فصل دراسي، و الاستعلام عن نتائج المواد التي درسها و أيضا الاستعلام عن المعدل التراكمي و غيرها من العمليات الخاصة بكل طالب، و أيضا يقوم قسم التسجيل في الجامعة بالتعامل مع أعضاء هيئة التدريس من خلال إعطاء تقارير عن الأقسام التي يقومون بتدريسها وغيرها من العمليات الخاصة بأعضاء هيئة التدريس، و أيضا يقوم النظام بتبادل الرسائل في بين مستخدمي هذا النظام. ولذلك ومع تزاحم و صعوبة الإجراءات للطلاب من اجل التسجيل، دعت الحاجة إلي تحويل النظام الحالي الموجود بالجامعة إلي نظام معتمد علي الانترنت بحيث يصل إليه جميع المستخدمين بكل سهوله و في أي مكان و أيضا يسهل عملية التسجيل للطلاب و الرد الآلي السريع لهم و إعطاء التقارير اللازمة، ويوزع العمل و الصلاحيات بين المستخدمين. Abstract Register net is a class registration system for universities Tripoli University. Students, advisors, and teachers will all be able to access the system. such activities that will be taking place are adding and dropping of classes, viewing class schedule, viewing classes to add, overriding registration, and viewing of an for universities transcript.
نجوى محمد خليفة الذيب (2012)

Abstract In this thesis, we present a set of scheduling algorithms that are used in designing core-based system-on-chips. Related techniques such as hardware /software codesign, and High-level-synthesis are defined. However, we selected some algorithms at system level and core level to implement them. They combined in system design methodology. Therefore, we used them for design exploration process. The methodology able to explore designs by scheduling them partitioning systems, and pipelining.Finally results obtained are encouraging to use the selected algorithm in designing efficient core-based system-on-chip systems.
مفيدة رمضان علي بلال (2010)

Abstract In practice, most SoCs are multiprocessor systems-on-chips (MPSoCs) because it is too difficult to design a complex system-on-chip without making use of multiple CPUs. MPSoCs are the latest picture of very large scale integration (VLSI) technology. The architecture of the system is generally tailored to the application rather than being a general-purpose chip. This in turn enforces designers to move beyond logic design into advanced computer architecture and parallel processing. In such architectures, cores are integrated via a custom or commercial interconnection network with a controller, timing and a function interface to the external world. Current state-of-the-art SoCs already embeds typical sub-systems such as digital signal processors (DSP), RAM, ROM, MPEG cores.The main goal of this thesis is to design an efficient switch for Fat-tree interconnection networks. In addition a useful survey study for interconnection networks architectures, technologies and routing algorithms was provided. The survey included in some details commonly used switching methods and virtual channel arrangements. The proposed switch structure has been validated by a software model.A set of algorithms and procedures have been developed to facilitate the switch functionality. Those procedures include the control of transmission of the packets from switch input buffer to switch output buffer and transferring packets from switch output buffer to neighboring switch input buffer. While the input/output link controllers take care of buffer assignments to flits (packet) and deals with buffer organization. More over, the algorithms include (i) the routing algorithm which is the least common ancestor routing algorithm, (ii) arbitration algorithm that based on round-robin technique.Therefore in this thesis we have proved the correctness of the functionality of the proposed switch in software model that have been written in C++ language. The obtained simulation results of the switch functionality in fat-tree of 16 nodes definitely declare the correctness of the proposed arbitration scheme as well as showing the efficiency of the routing algorithm. Finally, we can say that the fat-tree interconnection network is very good candidate to implement future NoC connectivity for current and future multiprocessor systems-on-chips (MPSoCs) designs due to its modular, flexible and regular structured design. In turn, these features are suitable as well for VLSI realizations.
أسماء شعبان العصار (2010)